Technology

BTQ, ICTK finish design of chip that embeds quantum-ready crypto and hardware IDs

BTQ Technologies and Korea’s ICTK said they have completed the design of a security chip that merges BTQ’s quantum-oriented compute-in-memory cryptographic engine with ICTK’s PUF device-identification technology, a combination intended to provide hardware-rooted authentication and crypto agility for IoT, AI and edge devices.

BTQ, ICTK finish design of chip that embeds quantum-ready crypto and hardware IDs
©Illustration AI Priya Sharma / news-block.org

BTQ Technologies and South Korea’s ICTK said they have completed the design of a new security chip that fuses a memory‑based cryptographic accelerator with a physically unclonable function to create a hardware-rooted identity and cryptographic engine for connected devices.

What the chip does

The device pairs BTQ’s Quantum Compute‑in‑Memory (QCIM) security intellectual property — a compact cryptographic accelerator that runs inside the memory subsystem — with ICTK’s VIA PUF™ technology, which derives a unique hardware identity from microscopic manufacturing variations. The collaborators said production preparation is now under way.

Why that matters: integrating a cryptographic block that minimizes data movement and power use with a built‑in, hardware-derived ID aims to give devices faster, lower‑power crypto operations while enabling unique device authentication at the silicon level. The companies position the design for use in IoT, AI devices, industrial systems, secure elements, edge devices and other connected infrastructure where long‑term cryptographic resilience and trusted device identity are critical.

How the technologies work

  • QCIM: a compute‑in‑memory architecture that executes cryptographic algorithms inside memory to reduce latency and energy associated with moving data between processors and memory.
  • PUF (VIA PUF™): a hardware technique that leverages unavoidable microscopic variations from chip manufacturing to produce a unique, hard‑to‑clone identifier for each device.

The combination is intended to deliver both cryptographic agility — the ability to support current and post‑quantum algorithms — and a trusted, device‑level identity without relying solely on externally stored keys.

Context and immediate consequences

As devices across consumer, industrial and critical infrastructure sectors become more interconnected, security architects are pushing cryptographic functions closer to hardware to reduce attack surfaces and improve performance. Embedding a PUF gives each chip an intrinsic identity that can be used for authentication and key provisioning, while compute‑in‑memory designs are being explored to address power and latency constraints on edge devices.

FeatureIntended benefit
Compute‑in‑memory (QCIM)Lower latency and power, less data movement
VIA PUF™Unique hardware identity, unclonable device fingerprint
Crypto‑agile designSupport for classical and post‑quantum algorithms

BTQ described QCIM as a "soft IP" cryptographic accelerator that can be integrated into diverse chip architectures to support both conventional and post‑quantum cryptography in a compact, low‑power block. ICTK’s PUF technology provides the device‑level authentication layer.

Production preparation signals the partners expect demand across a range of markets where trusted device identity and long‑lived cryptographic protections are becoming priorities: connected sensors and actuators, edge AI modules, industrial control systems and secure elements embedded in payment or identity products.

What to watch next

  • Whether the companies announce manufacturing partners and a commercial product timeline.
  • Adoption by device makers seeking on‑chip post‑quantum readiness and hardware‑rooted identity.
  • Independent security assessments verifying the PUF reliability and the QCIM block’s resistance to side‑channel and fault attacks.

For system designers and operators, the announcement underscores a broader industry shift toward tightly coupling authentication and cryptography at the silicon level to meet performance, power and resilience requirements as quantum threats and edge compute demands evolve.

Priya Sharma
Priya AI Technology Reporter online

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